Artificial intelligence is forcing us to accelerate the development of different technologies to improve their capabilities. One of those that would be being accelerated is the PCIe 7.0 interface, of which we have already seen a prototype from the company Cadence System. We have been able to see this PCIe 7.0 prototype that already allows speeds of 128 GT/s during PCI-SIG DevCon 2024.
You’re probably wondering what GT/s or Gigatransfers per second are. This information is important in PCIe interfaces, which is a serial bus with an integrated data clock. Data transmissions are encrypted.
PCIe 5.0 offers 32 GT/s with 128b/130b encoding. We have to send 128 bits of data, a 130-bit transfer with encryption is required. If we multiply the Gigatransfers by the coding (32 GT/x * [128b/130b]) we will have a speed of 31.5 GB/s.
PCIe 7.0 interface preview
You should know that the new version of the PCIe data bus is in full development phase. What has been shown is a preliminary prototype, there is still a long way to go before it is fully developed.
The PCI-SIG DevCon 2024 event, we can say, has been a great success for the Cadence company thanks to its prototype. During the event, they showed off their first IP solution for the new data transfer interface. Attendees at the event were able to see a demonstration of the TX and RX capabilities of PCIe Gen 7 with a speed of 128 GT/s. To achieve this, a linear optical connector has been used, obtaining low latency and no timing.
The company highlights that it has achieved a consistent pre-FEC BER transfer throughout the event that lasted two days. There have been no interruptions, which is a great milestone and gives plenty of room for improvement with this new technology.
Something quite interesting is that the PEM4 histogram of the receiver has shown good linearity and margin. We are talking about the first demonstration of transfer between TX and RX of 128 GT/s. Of course, this has required commercial optical connectors, unlike last year’s solution that required special communication media.
A great technical advance has been achieved to be able to offer these capabilities in a technology in the development phase. But it is not the only thing they have shown during the event, they have carried out different demonstrations about PCIe such as:
- PCIe 7.0 with optical connection.
- PCIe 7.0 electrical.
- Consecutive PCIe 6.0 RP/EP interface interoperability.
- PCIe 6.0 communication protocol in FLIT mode with Lecroy Exerciser.
- PCIe 6.0 communication protocol in FLIT mode.
- PCIe 6.0 JTOL data interface with Anritsu and Tektronix equipment.
- PCIe 6.0 communication protocol with Viavi Protocol Analyzer.
- Demonstration of PCIe 6.0 system-level interoperability with PCIe Gen5 platform.
A set of demonstrations by Cadence, which is an industry leader in the development of professional solutions based on PCIe. Although above all the progress in the development of PCIe 7 stands out, it also highlights the capabilities of PCIe 6. This last interface, most likely, will begin to be deployed next year in professional sectors such as Data Centers and AI systems.
